The present invention describes methods for migrating a software design tool to a new version of the tool, and more specifically, methods, computer programs and systems for using information obtained with the older version of the design tool to shorten the time required to obtain a compiled design with the new design tool.
Structured application-specific integrated circuits (ASIC) are sometimes used as alternatives to programmable logic devices (PLD) such as field-programmable gate arrays (FPGA). An FPGA has a generic structure that may include many identical blocks of logic circuitry, many registers, and a number of other types of circuit blocks such as I/O blocks, RAM blocks, DSP blocks, PLL/DLL blocks, etc. These various circuitries are programmable to perform any of a variety of tasks. An FPGA also has a generic interconnection structure. This structure is programmable to interconnect the other circuitries on the device in any of many different ways. The logic blocks of such an FPGA may be referred to as logic elements, logic modules, adaptive logic elements, or adaptive logic modules (“LEs”, “LMs”, “ALEs”, or “ALMs”).
A structured ASIC has a generic structure that includes many identical instances of a relatively simple circuit block (a so-called hybrid logic element or “HLE”). The structured ASIC may also generically include other blocks that are comparable to the special-purpose blocks on a related FPGA (e.g., I/O blocks, RAM blocks, PLL/DLL blocks, etc.). Efficient and reliable conversion from FPGA designs to structured ASIC designs, and vice versa, can be beneficial in a variety of contexts. For example, after an FPGA implementation of a design has been in use for awhile, a user may desire to migrate that design to a functionally equivalent ASIC in order to lower unit costs. As another example, the user may desire to use an FPGA to prototype a design that is intended for ASIC implementation. Again, the FPGA and ASIC must be functionally equivalent for such prototyping to be meaningful.
Circuit developers use different PLDs in the different stages of development depending on the time required to program the PLDs and the volume desired. Because of the relationship between these PLDs, circuit design tools leverage some of the information obtained in the compilation of the PLD, to obtain a compiled design for the other PLD in the family.
The problem of having to compile designs for two different PLDs gets accentuated when the circuit designer rolls the circuit design to a new version of software. Typically, new compilations for the circuit designs are required due to the changes in the software, such as the newer versions of the libraries used by the software. Taking into account that some of the larger designs may require days, or even weeks to be compiled, rolling a new software version and having to recompile all the designs entails a large amount of work and production delays.
It is in this context that embodiments of the invention arise.